
.equ pattern1_rt, 0x55555555
.equ pattern2_rt, 0xAAAAAAAA

.global IEC60730_CPU_Reg_Test_RunTime

IEC60730_CPU_Reg_Test_RunTime:
@push registers to stack
	push	{r0-r7}

@disable all interrupt
	mrs		r0, CPSR
	push	{r0-r7}
	and		r0, r0, #0xFFFFFF3F	 @I-bit(7), F-bit(6) disabled
	msr		CPSR_c, r0
	mrs		r0, CPSR 			@ for checking CPSR

@===========R0 Test=============
@R0 test
@compare bit 0-7
	movs	r0, #0xAA
	cmp		r0, #0xAA
	bne     _test_r0_fail_rt
	movs	r0, #0x55           @For SW test breakpoint
	cmp		r0, #0x55
	bne     _test_r0_fail_rt

@compare bit 8-15
	ldr		r0, =0x0000AA00
	lsrs    r0, r0, #8
	cmp		r0, #0xAA
	bne     _test_r0_fail_rt
	ldr		r0, =0x00005500
	lsrs    r0, r0, #8
	cmp		r0, #0x55
	bne     _test_r0_fail_rt

@compare bit 16-23
	ldr		r0, =0x00AA0000
	lsrs    r0, r0, #16
	cmp		r0, #0xAA
	bne     _test_r0_fail_rt
	ldr		r0, =0x00550000
	lsrs    r0, r0, #16
	cmp		r0, #0x55
	bne     _test_r0_fail_rt

@compare bit 24-31
	ldr		r0, =0xAA000000
	lsrs    r0, r0, #24
	cmp		r0, #0xAA
	bne     _test_r0_fail_rt
	ldr		r0, =0x55000000
	lsrs    r0, r0, #24
	cmp		r0, #0x55
	bne     _test_r0_fail_rt
	b		_reg_test_r1_r7_rt

_test_r0_fail_rt:
@enable interrupt
	pop		{r0-r7}
	msr		CPSR_c, r0
	mrs		r0, CPSR
@restore registers
    pop     {r0-r7}

@==test fail==
    movs    r0, #0x00
@branch back
	bx      lr
@===============================

@=========R1 - R7 Test==========
_reg_test_r1_r7_rt:
	ldr		r1, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r1, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r1, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r1, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r2, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r2, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r2, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r2, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r3, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r3, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r3, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r3, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r4, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r4, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r4, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r4, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r5, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r5, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r5, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r5, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r6, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r6, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r6, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r6, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r7, =pattern1_rt
	ldr		r0, =pattern1_rt        @For SW test breakpoint
	cmp		r7, r0
	bne 	_test_r1_r7_fail_rt
	ldr		r7, =pattern2_rt
	ldr		r0, =pattern2_rt        @For SW test breakpoint
	cmp		r7, r0
	bne 	_test_r1_r7_fail_rt
	b		_test_cpu_reg_pass_rt

_test_r1_r7_fail_rt:
@enable interrupt
	pop		{r0-r7}
	msr		CPSR_c, r0
	mrs		r0, CPSR
@restore registers
    pop     {r0-r7}

@==test fail==
    movs    r0, #0x00
@branch back
	bx      lr
@===============================

_test_cpu_reg_pass_rt:
@   ldr     r1, =u8CPUTestPass
@   movs    r0, #0x01
@   str     r0, [r1]
	pop		{r0-r7}
	msr		CPSR_c, r0
	mrs		r0, CPSR
@restore registers
	pop     {r0-r7}

@==test pass==
    movs    r0, #0x01

@branch back
	bx      lr
	NOP